1. Field of the Invention
The present invention relates to a cache controller and a cache control method for writing data to a cache memory. The invention particularly relates to a cache controller and a cache control method that enable retrieval of large amounts of data to be written to a cache memory, while achieving downsizing and cost reduction of a chip.
2. Description of the Related Art
Recently, most information processing apparatuses such as computers include a central processing unit (CPU) incorporating a cache memory to improve the processing speed of the CPU by reducing the number of accesses to a main memory generally having low access speed. A cache memory is accessible at high speed. However, because the cache memory has a smaller size than that of the main memory, the cache memory does not always store therein data required by the CPU (i.e., cache miss). In such a case, data stored in an upper-level cache such as a secondary cache or in the main memory needs to be moved in the cache memory on the CPU.
In general, data to be moved in the cache memory is temporarily retrieved in a data register connected to the cache memory, and then written to the cache memory from the data register.
Recent years have seen remarkable technological developments that increase the processing speed of CPUs and also the size of main memories. As a result, a CPU requires more data per unit time, while taking a longer time to retrieve the data from the main memory. This causes a speed discrepancy between the CPU and the main memory, thus relatively increasing memory latency.
Under such circumstances, proper control for moving data into a cache memory is important. For example, Japanese Patent Application Laid-open No. H7-210460 discloses a technology that reduces the amount of data to be moved-in when a main memory has increased loads, and that resumes a move-in of data having an equivalent amount to the reduced data when the load of the main memory becomes smaller.
The technology disclosed in Japanese Patent Application Laid-open No. H7-210460 can efficiently adjust the data move-in when a cache miss occurs. However, the CPU using the data to be moved-in runs at a processing speed limited by the speed of the main memory, thus the technology cannot offset the increased memory latency completely. In this case, the CPU may execute subsequent processes one after another, while performing the move-in of the data for handling the cache miss to improve throughput. This may cause more cache misses simultaneously, increasing the amount of data to be moved-in. Thus, there is a demand to increase the amount of data retrievable at one time by a data register that writes data to the cache memory.
When a data queue in the data register is simply expanded to increase the size of the data register, the data queue dimensionally exceeds a current chip. This is unrealistic because such a chip on which a CPU is mounted needs to have a larger size opposing the downsizing of the chip.
Alternatively, a low cost random access memory (RAM) may be used as a substitute for the data register. Because the data register holds data to be written to the cache memory only temporarily, the RAM serving as a substitute for the data register only needs to have a significantly small size compared with the cache memory. To improve throughput with the RAM having such a small size and serving as a substitute for the data register, the amounts of inflow data and outflow data to and from the RAM per unit time need to be increased according to the amount of data to be written to the cache memory. As a result, a control circuit and a data bus used for the RAM occupy a large area, causing an increase in space and cost of the portion substituting for the data register.